The present invention is generally directed to the manufacture of a semiconductor device. In particular, the present invention relates to a process that provides for enhanced electrostatic discharge (ESD) protection in input/output transistors.
Silicidation of diffusion and gate regions of MOS transistors is commonly used in sub-micron technologies to minimize electrical resistance. A serious consequence is the possible degradation of ESD performance. During an ESD event, the transistor is stressed with a large drain voltage. If this voltage exceeds a first breakdown voltage (Vt1) for the transistor, a drain snapback current flows. During this breakdown the transistor does not function as intended. It can resume normal operation once the ESD event is over. As soon as the current begins flowing, the drain voltage drops. However, if the ESD event is severe enough a second breakdown voltage (Vt2) is crossed, at which point the transistor is destroyed.
One approach to ESD resistance is to provide a large area for breakdown current to flow. This slows the excursion to Vt2, which in many cases can mean the device escapes destruction. A common technique to provide a large area for breakdown current to flow is to selectively prevent the silicidation on the drain side of input/output drivers. Having no silicidation adds extra diffusion resistance to the circuit. The extra diffusion resistance allows the current to be distributed across the full device width. It enables the circuit to share the ESD current discharge among all the structure on the MOS driver.
One conventional silicide blocking technique uses one or more additional dielectric layers that are deposited after the source and drain (S/D) implants and the subsequent rapid thermal annealing (RTA). A mask is applied and the dielectric is etched off everywhere on the wafer except where silicide exclusion is desired, usually in the I/O devices. A silicide, such as titanium silicide (TiSix), does not form on the dielectric. In an example process, the etch is done in two steps, a dry etch in a plasma followed by a wet etch to avoid damage to the silicon. The photomask is removed by conventional stripping. However, this approach often leads to increased junction or device leakage in non-excluded devices, namely the core devices. This leakage is caused by an attack on the isolation or spacer material during etching of the silicide exclusion. Device leakage affects the transistor""s ability to receive and maintain an electric charge and is of particular importance for semiconductor memory. For example, the transistor holding a charge may represent a bit of data in the memory. The bit of data should not change state unless it is intended to change.
Refer to FIG. 1A. A conventional process to selectively silicide the source/drain regions of a MOS transistor may begin after the Nldd and Pldd masking and implanting steps of 5 and 10. To protect the gate a spacer deposition 15 forms a dielectric spacer on the gate regions. Undesired areas of the spacer are removed in a post spacer clean process 20. The N+ and P+ masking and implanting steps 25 and 30 provide the electrical connections to the source/drain regions. A rapid thermal anneal (RTA), 35 drives and activates the implant species. The process that enables the selective silicidation occurs in steps 40a-40e. Another dielectric deposition 40a, covers the features of the MOS substrate. A silicide-blocking mask 40b covers areas in which the dielectric deposition 40a is to remain. Other areas, such as source/drain regions in which it is desired to have silicide, are exposed. A dry etch 40c and a wet etch 40d etch the exposed regions. A resist strip 40e removes the photo resist. The substrate undergoes a pre-cleaning 45 prior to the refractory metal deposition 50. In many processes, titanium or cobalt is used. Areas upon which the silicide blocking mask 40b is present, do not silicide. However, the selective silicidation adds a significant number of steps 40a-40e that may not be present in a process not having selective silicidation. The resulting structure is depicted in FIG. 1B.
Refer to FIG. 1B. An example input MOS structure 100 has been fabricated with silicide blocking. It may include a substrate 110 and a P-well 120 surrounded by trench isolation regions 130. The implant regions 140 and 140a are the lightly doped drain (LDD) and N+ implants respectively. The poly-silicon gate 170, is protected by dielectric spacers 160. A silicide blocking layer 180, protects the implant regions 140,and 140a from silicide 150. After the silicidation, a dielectric layer 190 is deposited on the device. Contact regions 200 are defined in the dielectric layer 190 to connect the device via the silicided regions 150 to conductive lines 210.
As in the aforementioned selective masking technique, having no silicidation adds extra diffusion resistance to the circuit, allowing the current to distribute across the device width. It enables the circuit to share the ESD current discharge among all the structure on the NMOS driver.
However, the technique increases the complexity of the device processing in that additional masking and etching steps oftentimes are used to implement the selective silicidation of source/drain regions. The extra processing steps increase product costs and may affect device reliability.
Another silicide blocking technique is outlined in U.S. Pat. No. 5,413,969 titled xe2x80x9cDifferential Treatment to Selectively Avoid Silicide Formation on ESD I/O Transistors in a Salicide Process,xe2x80x9d issued to T. Y. Huang on May 9, 1995 and assigned to VLSI Technology, Inc. and incorporated by reference, herein. The technique involves differentially treating source/drain regions of, for example, input transistors and input/output (I/O) transistors of a device, by selectively implanting species, such as arsenic into source/drain regions of the I/O transistors in which is not desired to form silicide. Titanium is deposited on both the source/drain regions and then annealed at a temperature that forms a silicide in the non-implanted regions. After annealing, the unreacted metal is stripped off the implanted regions.
There exists a need to be able to selectively block silicidation in I/O transistors to enhance ESD performance, maintain the performance of the core transistors, and minimize product costs.
The present invention is exemplified in a number of implementations, two of which is summarized below. A modification to the application of a spacer dielectric to the gate region of a MOS transistor enables the formation of the dielectric spacer to selectively block the silicidation of areas on the transistor and to block areas from ion implantation. In accordance with an embodiment of the invention, a method selectively blocks silicidation of a MOS transistor structure. The MOS structure has a substrate area of a first polarity type, a source and drain region of a second polarity type and a silicon gate over a thin oxide on the substrate area. The method comprises depositing a spacer dielectric that covers the MOS structure. The spacer dielectric is then masked to define silicidation blocking regions and silicidation accepting regions. In silicidation accepting regions, the spacer dielectric is removed. An additional feature of this embodiment is that species are implanted in the silicidation accepting regions. The MOS transistor structure is then annealed to activate the species. The silicide-accepting regions have a refractory metal deposited thereon. Again, the MOS structure is annealed to form the refractory metal silicide. These silicide-accepting regions may be the gate, source or drain of the MOS transistor structure.
In accordance with another embodiment of the present invention, an MOS transistor comprises a source region of a first polarity type and a drain region having a first implant region of a first polarity type. A gate region has a spacer dielectric disposed upon a predetermined portion thereof and it covers a predetermined portion of the first implant region. The spacer dielectric also partially extends to a drain contact within the drain region. The drain contact has a second implant region of a first polarity type substantially within the first implant region. A channel region of a second polarity is below the gate. The channel region includes a channel adjacent the gate and extends between the source region and drain region. An additional feature of this embodiment is that the spacer dielectric may be of the following dielectrics, silicon oxide, silicon-rich oxide, and silicon nitride.